PTL 1 discloses an SiC semiconductor device having a JFET with a trench structure. The JFET is formed as follows.
After an n− type drift layer, a p+ type first gate region, and an n+ type source region have been formed on an n+ type SiC substrate in the stated order, a trench that penetrates through those regions is formed. Then, an n− type channel layer and a p+ type second gate region are allowed to epitaxially grow within the trench, and embedded within the trench. Thereafter, a substrate surface is planarized, and unnecessary portions of the n− type channel layer and the p+ type second gate region are removed to expose the n+ type source region. Subsequently, the substrate surface is etched with the use of a mask for exposing an outer peripheral region that surrounds a cell region in which the JFET is configured. The n+ type source region is removed in the outer peripheral region, and a first concave portion is formed in the outer peripheral region to form a first mesa portion.
Further, the substrate surface is etched with the use of a mask for exposing an outer edge of the first mesa portion in the outer peripheral region, the p+ type first gate region is further removed, and a second concave portion is formed within the first concave portion to form a second mesa portion. Thereafter, after a p type surface electric field relaxation (resurf) layer has been formed at a boundary position between a side surface and a bottom surface of the second concave portion, or ion implantation for forming a p type guard ring layer is conducted on the bottom surface of the second concave portion, the bottom surface of the second concave portion is activated through a heat treatment. In addition, the JFET disclosed in PTL 1 is formed through a process of forming an interlayer insulating film on a substrate front surface side, a process of forming a gate electrode and a source electrode, and a process of forming a drain electrode on a substrate rear surface side.